The present invention relates generally to the fabrication of integrated circuits. More particularly, the present invention relates to a process for fabricating contacts for integrated circuit devices.
Contacts are required in an integrated circuit device to provide electrical connections between layers or levels of the integrated circuit device. Semiconductor devices typically include a multitude of transistors which are coupled together in particular configurations through the use of contacts.
In a conventional flash memory cell, a memory cell includes a stacked gate, a drain, and a source. A drain contact electrically connects the drain of the memory cell to a conductive layer (a bit line) above the stacked gate. The conductive layer can be a polysilicon layer, first metal layer, or other layer utilized to connect a bit line to a storage node (drain) of the memory cell.
Additionally, the source of the memory cell is often coupled to a source line with a VSS implant (e.g., a VSS connector or a self-aligned source (SAS) module). Sources of neighboring transistors are coupled together at the substrate level (in the active region). The SAS module is typically fabricated according to the following steps: a SAS mask and etch of LOCOS oxide, a VSS connection mask and implant. Module fabrication requires two critical masking steps, one during the SAS mask and etch and another during the VSS connection mask and implant.
The fabrication steps related to the SAS module can be somewhat disadvantageous. Etching steps can cause charge damage in the active region. Also, the SAS module can be disadvantageous due to its sheet resistance and size.
Contacts associated with the flash memory cell must be spaced from the polysilicon associated with the stacked gate. As feature sizes are reduced according to integrated circuit processes, smaller dimensions are required to achieve higher packing densities. Generally, contacts must be spaced apart from the stacked gate so alignment errors do not result in a shorting of the stacked gate with the source contact or the drain contact. The spacing between the contact and gate contributes to the overall size of the flash memory cell.
Thus, there is a need to eliminate the need for a SAS module. Further, there is a need to relax contact to gate spacing requirements. Further still, there is a need for a flash memory with a smaller cell size. Further still, there is a need to reduce VSS source line resistance.
The present invention relates generally to a method of fabricating a contact for a transistor. The transistor has a stacked gate, a source, and a drain. The method includes depositing an etch stop layer over the stacked gate, the drain, and the source, depositing a first interlevel dielectric layer over the etch stop layer, etching the first interlevel dielectric layer and the etch stop layer from above the source and drain, depositing a first conductive material above the source and the drain, planarizing the first conductive material to a first level approximate a second level of the first interlevel dielectric layer, depositing a second interlevel dielectric layer above the first conductive material, etching the second interlevel dielectric layer to form a contact hole above the drain, and filling the contact hole with a second conductive material to form the contact. The method allows the contact to overlap or butt against the gate.
The present invention further relates to a method of fabricating an integrated circuit on a semiconductor substrate. The semiconductor substrate includes at least one stacked gate disposed between a source and a drain. The stacked gate includes a first barrier layer. The method includes depositing an insulative layer over the stacked gate, etching the insulative layer to leave insulative side wall spacers for the stacked gate, depositing a second barrier layer over the stacked gate, depositing a first interlevel dielectric layer over the second barrier, etching the first interlevel dielectric layer and the second barrier layer in accordance with a self-aligned contact mask, depositing a first conductive material above the source and the drain, depositing a second interlevel dielectric layer above the first conductive material, and forming a contact through the second interlevel dielectric layer. The contact is electrically coupled to the first conductive material.
The present invention even further relates to a method of fabricating an integrated circuit on a semiconductor substrate. The semiconductor substrate includes at least one gate disposed between a source and a drain. The method includes depositing a barrier layer over the gate, the source, and the drain, depositing a first interlevel dielectric layer over the first barrier layer, etching the first interlevel dielectric layer and the first barrier layer in accordance with a self-aligned contact mask, depositing a first conductive material over the source and the drain, depositing a second interlevel dielectric layer above the first conductive material and the first interlevel dielectric layer, and forming a contact through the second dielectric layer. The contact is electrically coupled to the first conductive material. The first interlevel dielectric layer and the barrier layer are removed from above the source and above the drain when the first interlevel dielectric layer is etched.
According to one exemplary aspect of the present invention, a local interconnect and self-aligned contact process replaces a self-aligned source (SAS) etch/implant module process for relaxed lithographic requirements. A single local interconnect mask replaces two critical masks. Generally, the conventional source line associated with flash memory devices can be moved from the active region to the local interconnect level. The process advantageously allows simultaneous formation of the drain contact and the VSS source line with a single local interconnect process.
In accordance with another exemplary embodiment of the present invention, the local interconnect process forms the drain contact and VSS source line via interlayer dielectric deposition/planarization, local interconnect etch, and tungsten (W) plug formation steps. Since the same etch stop layer is utilized for the local interconnect and for the contact etch, relaxed local interconnect and contact size can be maintained while achieving the same cell size. The disadvantages associated with the fabrication of the SAS module are reduced or eliminated.
In accordance with yet another exemplary embodiment of the present invention, spacings between gates and VSS source lines and between gates drain contacts are reduced. The reduced spacings allow larger contact sizes, thereby allowing less stringent lithographic requirements. In one embodiment, the contact can even butt against or overlap the gate.